China's Domestic Front-End Lithography Platform Shows Interim Results as AI Chip Roadmaps Update

Highlights

• SMEE exhibits model of next-generation front-end dry lithography platform
• Tesla's SI6 targets 80x HW4 compute; Dojo D3 shifts to chiplets
• TSMC denies developing 3D DRAM, reaffirms focus on logic foundry

Domestic Lithography Equipment: From "Deliverable" to "Platformized"

At the ninth China International Import Expo, Shanghai Micro Electronics Equipment (SMEE) displayed a model of its self-developed next-generation front-end dry lithography general technology platform. According to the official description, the platform supports both mainstream DUV technology routes, I-line (365nm) and KrF (248nm). Its high-precision objective lens and illumination system, high-speed dual wafer stage and mask stage, automated material transport system, and alignment and leveling sensor system are all self-reliant across the full chain. SMEE says the imaging performance of its domestic front-end dry lithography machines is now comparable to leading international products of the same class, with overlay accuracy and throughput closely catching up to international benchmarks. Multiple tools have run stably for long periods on production lines at leading domestic logic and memory fabs, supporting cumulative wafer runs of more than 10 million, with an effective operating rate above 92%. (Source: ITHome)

It is important to distinguish that what was shown this time is a "general technology platform model," not an announcement of mass production and delivery of a new model. Dry lithography serves mature process nodes and remains a tier below the ArF immersion (193nm) technology dominated by ASML. But the phrasing "platformized + full-chain self-reliance" is noteworthy: it means the competitive focus of domestic equipment is shifting from whether a single tool can run to architectural standardization and line replicability. The 92% effective operating rate is a production-line metric, and says more about usability than specs do, though the statistical basis and sample scope were not disclosed in the source material. (Source: ITHome)

AI Chips: Tesla Splits Inference and Training Into Two Routes

Tesla updated its AI accelerator roadmap and introduced the "SI (Super Intelligence)" naming. The plan shows: SI5/AI5 uses TSMC 3nm or Samsung 2nm with multi-chip module packaging, delivering 40x the compute of SI4; SI6/AI6 is 2nm-class with multi-chip modules, targeting 80x the compute of SI4, with GDDR7 memory (TBD) and 144GB. On the training side, Dojo D3 abandons the D1 wafer-scale system (SoW) architecture in favor of a multi-chiplet design using 2.5D+3D packaging with stacked HBM; its status is "in development." (Source: ITHome)

The most substantive change in the roadmap is Dojo's pivot: from a wafer-scale approach relying on distributed on-die SRAM to a conventional advanced packaging path of chiplets plus HBM. This contrasts with Musk's August 2025 cancellation of the wafer-scale Dojo project and his August 2026 statement that Nvidia hardware would be used, indicating that architecture choices for in-house training chips are converging toward the industry mainstream. But D3's process node is "TBD" and its memory is "TBD," leaving timing and yield still blank. (Source: ITHome)

Foundry Boundaries: TSMC Denies Touching DRAM

The Information reported that, at Nvidia's request, TSMC had begun planning a 3D DRAM manufacturing business, overseen by Xu Guojin, the vice president in charge of advanced packaging. A TSMC spokesperson denied the claim to Tom's Hardware, stressing that the company has always focused on its core business of specialized integrated circuit foundry. The report also noted that 3D DRAM would still take years for memory makers such as Micron, Samsung and SK Hynix to mass-produce; even if TSMC proceeded, it could not ease the current memory shortage within at least five years. (Source: ITHome)

The value of this thread lies not in "whether it is really happening" but in the industry pressure it exposes: AI demand is driving up DRAM prices, and memory is turning from an ordinary commodity into a strategic resource that affects delivery, which is why the leading logic foundry keeps being asked whether it is overstepping. TSMC's denial maintains its "pure foundry" positioning, but it also means there is no foundry-side solution to the near-term memory shortage. (Source: ITHome)

Other Developments

• Alphabet, Google's parent company, spent about $548 million building a stake in Qualcomm, betting on the AI data center chip segment. (Source: TMTPost)
• Device-side chip updates: the Asus Zenbook 16 Air Snapdragon edition packs a 3nm Snapdragon X2 Elite Extreme with an 18-core CPU and 80 TOPS NPU, 24GB+1TB at 12,499 yuan; the Dangbei H5 second-generation TV box upgrades to the Allwinner H626 at 469 yuan; the Motorola Razr Flex 27 is said to get a China version with the fifth-generation Snapdragon 8. (Source: ITHome)